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1.Consider a dynamic RAM that must be given a refresh cycle 64 times per ms. Each refresh operation requires 150 ns; a memory cycle requires 250 ns. What percentage of the memory’s total operating time must be given to refreshes?
A block direct mapping cache has lines/slot that contains 4 words of data
The cache size is 64Kline and the main memory capacity is 16Mbytes.
a. How many bits are used for main memory address?
b. How many bits for words in cache?
c. How many bits for lines/slots in cache?
d. Draw the format for main memory address by specifying the size of tag, line/slot and word.
e. Given the following main memory address 3AFF80h, find the values for tag, line/slot and word field in hexadecimal.
f. What is line size (cache word/cache block size)?
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